From bd068399357f6bafee6b3fe185d818a6e0c401fe Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 11 Jul 2026 21:36:19 +0800 Subject: [PATCH 1/3] fix(linker): correct cross-toolchain memory map inconsistencies Found by cross-checking each example's GCC (STM32CubeIDE)/IAR (EWARM)/ Keil (MDK-ARM) linker scripts against each other and against known-good Templates sibling projects, following the same audit already done for STM32CubeG0/G4/H5/H7/L0/L4/L5/U5/WB/WBA/WL/F0/F1/F4/F7 in this repo family. 1. Applications/OpenBootloader (NUCLEO-C031C6, STM32C031C6, 32K flash total): GCC's .ld declared a 27K bootloader region; IAR's .icf (ROM_end 0x08003BFF) and Keil's top-level / tags both agree on 15K (0x3C00). Keil's OCR_RVCT4 entry had drifted to 0x8000 (32K, exactly the whole chip - a giveaway that it was never customized from the device-pack default), disagreeing with its own top-level IROM tag in the same file. Fixed GCC's .ld to 15K and Keil's OCR_RVCT4 Size to 0x3c00 to match IAR and Keil's own top-level tag. 2. Applications/FileX/Fx_SRAM_File_Edit_Standalone and Applications/ThreadX/Tx_LowPower and Tx_Thread_Creation (NUCLEO-C092RC, STM32C092RC, 256K flash / 30K RAM): all three projects' GCC .ld and Keil .uvprojx (both the summary line and the IRAM/IROM/OCR_RVCT4 fields) declared only 128K flash / 24K RAM - half of the chip's actual capacity on the flash side and less than the actual RAM. This board's own Templates project confirms the real 256K/30K split. Fixed GCC's .ld MEMORY block and Keil's line + IRAM/IROM/OCR_RVCT4/OCR_RVCT9 entries on all three projects to match. No local ARM toolchain (arm-none-eabi-gcc/IAR/Keil) available to compile/link-test these changes; verification relied on address-arithmetic cross-referencing against multiple independent references per finding (Templates gold standards, IAR's region boundaries, and Keil's own top-level IROM/Cpu tags vs its OCR_RVCT entries within the same file). Signed-off-by: 94xhn <87560781+94xhn@users.noreply.github.com> --- .../OpenBootloader/MDK-ARM/OpenBootloader.uvprojx | 2 +- .../OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld | 2 +- .../MDK-ARM/Fx_SRAM_File_Edit_Standalone.uvprojx | 10 +++++----- .../STM32CubeIDE/STM32C092RCTX_FLASH.ld | 8 ++++---- .../ThreadX/Tx_LowPower/MDK-ARM/Tx_LowPower.uvprojx | 10 +++++----- .../Tx_LowPower/STM32CubeIDE/STM32C092RCTX_FLASH.ld | 8 ++++---- .../MDK-ARM/Tx_Thread_Creation.uvprojx | 10 +++++----- .../STM32CubeIDE/STM32C092RCTX_FLASH.ld | 8 ++++---- 8 files changed, 29 insertions(+), 29 deletions(-) diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx index 3d61c551..2e917482 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx @@ -276,7 +276,7 @@ 1 0x8000000 - 0x8000 + 0x3c00 1 diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld index 6252b9ac..1e1c561d 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld @@ -46,7 +46,7 @@ MEMORY { RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 5K RAM2 (xrw) : ORIGIN = 0x20001400, LENGTH = 1K - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 27K + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 15K } /* Sections */ diff --git a/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/MDK-ARM/Fx_SRAM_File_Edit_Standalone.uvprojx b/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/MDK-ARM/Fx_SRAM_File_Edit_Standalone.uvprojx index 5c91f202..b9d44e17 100644 --- a/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/MDK-ARM/Fx_SRAM_File_Edit_Standalone.uvprojx +++ b/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/MDK-ARM/Fx_SRAM_File_Edit_Standalone.uvprojx @@ -18,7 +18,7 @@ STMicroelectronics Keil.STM32C0xx_DFP.1.2.0-RC2 https://www.keil.com/pack/ - IRAM(0x20000000-0x20005FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ + IRAM(0x20000000-0x200077FF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ @@ -247,12 +247,12 @@ 0 0x20000000 - 0x6000 + 0x7800 1 0x8000000 - 0x20000 + 0x40000 0 @@ -277,7 +277,7 @@ 1 0x8000000 - 0x20000 + 0x40000 1 @@ -302,7 +302,7 @@ 0 0x20000000 - 0x6000 + 0x7800 0 diff --git a/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/STM32CubeIDE/STM32C092RCTX_FLASH.ld b/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/STM32CubeIDE/STM32C092RCTX_FLASH.ld index 203d0970..3e7ad16b 100644 --- a/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/STM32CubeIDE/STM32C092RCTX_FLASH.ld +++ b/Projects/NUCLEO-C092RC/Applications/FileX/Fx_SRAM_File_Edit_Standalone/STM32CubeIDE/STM32C092RCTX_FLASH.ld @@ -6,8 +6,8 @@ ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32C092RCTx Device from STM32C0 series -** 128KBytes FLASH -** 24KBytes RAM +** 256KBytes FLASH +** 30KBytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. @@ -44,8 +44,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 30K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K } /* Sections */ diff --git a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/MDK-ARM/Tx_LowPower.uvprojx b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/MDK-ARM/Tx_LowPower.uvprojx index 9b9ed203..03fdf77f 100644 --- a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/MDK-ARM/Tx_LowPower.uvprojx +++ b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/MDK-ARM/Tx_LowPower.uvprojx @@ -18,7 +18,7 @@ STMicroelectronics Keil.STM32C0xx_DFP.1.2.0-RC2 https://www.keil.com/pack/ - IRAM(0x20000000-0x20005FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ + IRAM(0x20000000-0x200077FF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ @@ -247,12 +247,12 @@ 0 0x20000000 - 0x6000 + 0x7800 1 0x8000000 - 0x20000 + 0x40000 0 @@ -277,7 +277,7 @@ 1 0x8000000 - 0x20000 + 0x40000 1 @@ -302,7 +302,7 @@ 0 0x20000000 - 0x6000 + 0x7800 0 diff --git a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/STM32CubeIDE/STM32C092RCTX_FLASH.ld b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/STM32CubeIDE/STM32C092RCTX_FLASH.ld index 203d0970..3e7ad16b 100644 --- a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/STM32CubeIDE/STM32C092RCTX_FLASH.ld +++ b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_LowPower/STM32CubeIDE/STM32C092RCTX_FLASH.ld @@ -6,8 +6,8 @@ ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32C092RCTx Device from STM32C0 series -** 128KBytes FLASH -** 24KBytes RAM +** 256KBytes FLASH +** 30KBytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. @@ -44,8 +44,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 30K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K } /* Sections */ diff --git a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/MDK-ARM/Tx_Thread_Creation.uvprojx b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/MDK-ARM/Tx_Thread_Creation.uvprojx index 31195de3..e4935d7a 100644 --- a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/MDK-ARM/Tx_Thread_Creation.uvprojx +++ b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/MDK-ARM/Tx_Thread_Creation.uvprojx @@ -18,7 +18,7 @@ STMicroelectronics Keil.STM32C0xx_DFP.1.2.0-RC2 https://www.keil.com/pack/ - IRAM(0x20000000-0x20005FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ + IRAM(0x20000000-0x200077FF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ @@ -247,12 +247,12 @@ 0 0x20000000 - 0x6000 + 0x7800 1 0x8000000 - 0x20000 + 0x40000 0 @@ -277,7 +277,7 @@ 1 0x8000000 - 0x20000 + 0x40000 1 @@ -302,7 +302,7 @@ 0 0x20000000 - 0x6000 + 0x7800 0 diff --git a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/STM32CubeIDE/STM32C092RCTX_FLASH.ld b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/STM32CubeIDE/STM32C092RCTX_FLASH.ld index 203d0970..3e7ad16b 100644 --- a/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/STM32CubeIDE/STM32C092RCTX_FLASH.ld +++ b/Projects/NUCLEO-C092RC/Applications/ThreadX/Tx_Thread_Creation/STM32CubeIDE/STM32C092RCTX_FLASH.ld @@ -6,8 +6,8 @@ ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32C092RCTx Device from STM32C0 series -** 128KBytes FLASH -** 24KBytes RAM +** 256KBytes FLASH +** 30KBytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. @@ -44,8 +44,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 30K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K } /* Sections */ From 692706ba8a4d6dd117bcee01124541c79aa214a6 Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 18 Jul 2026 04:15:50 +0800 Subject: [PATCH 2/3] Align C031C6 flash sizing with maintainer-confirmed board capacity The review accepted the NUCLEO-C092RC fixes but called out the two NUCLEO-C031C6 flash-size edits. This follow-up keeps the C092RC corrections and updates only the reviewed C031C6 locations to 32K. Constraint: Keep the accepted NUCLEO-C092RC changes untouched Rejected: Normalize the remaining C031C6 linker metadata drift | outside the review scope for this PR Confidence: high Scope-risk: narrow Directive: Do not broaden this PR beyond the two maintainer-requested C031C6 flash entries without a fresh review discussion Tested: git diff --check; targeted diff inspection; static 0x8000 equals 32K address-range check Not-tested: full project builds for the IDE-specific linker/config files --- .../MDK-ARM/OpenBootloader.uvprojx | 1344 ++++++++--------- .../STM32CubeIDE/STM32C031C6TX_FLASH.ld | 400 ++--- 2 files changed, 872 insertions(+), 872 deletions(-) diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx index 2e917482..7d21a0d3 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx @@ -1,673 +1,673 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - NUCLEO-C031C6 - 0x4 - ARM-ADS - 6160000::V6.16::ARMCLANG - 1 - - - STM32C031C6Tx - STMicroelectronics - Keil.STM32C0xx_DFP.1.0.0 - http://www.keil.com/pack - IROM(0x08000000-0x8003BFF) IRAM(0x20000000-0x200017FF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ - - - - 0 - - - - - - - - - - - $$Device:STM32C031C6Tx$CMSIS\SVD\STM32C031.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - NUCLEO-C031C6\Exe\ - Project - 1 - 0 - 1 - 1 - 1 - - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 1 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - SARMCM3.DLL - -REMAP - DARMCM1.DLL - -pCM0+ - SARMCM3.DLL - - TARMCM1.DLL - -pCM0+ - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4101 - - 1 - BIN\UL2V8M.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0+" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x1800 - - - 1 - 0x8000000 + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + NUCLEO-C031C6 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32C031C6Tx + STMicroelectronics + Keil.STM32C0xx_DFP.1.0.0 + http://www.keil.com/pack + IROM(0x08000000-0x8003BFF) IRAM(0x20000000-0x200017FF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ + + + + 0 + + + + + + + + + + + $$Device:STM32C031C6Tx$CMSIS\SVD\STM32C031.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + NUCLEO-C031C6\Exe\ + Project + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 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../Core/Inc;../OpenBootloader/App;../OpenBootloader/Target;../../../../../Drivers/CMSIS/Device/ST/STM32C0xx/Include;../../../../../Drivers/CMSIS/Include;../../../../../Drivers/STM32C0xx_HAL_Driver/Inc;../../../../../Middlewares/ST/OpenBootloader/Core;../../../../../Middlewares/ST/OpenBootloader/Modules/I2C;../../../../../Middlewares/ST/OpenBootloader/Modules/Mem;../../../../../Middlewares/ST/OpenBootloader/Modules/USART - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - - - - - - - - - - - - - - - Application/Core - - - main.c - 1 - ../Core/Src/main.c - - - stm32c0xx_hal_msp.c - 1 - ../Core/Src/stm32c0xx_hal_msp.c - - - stm32c0xx_it.c - 1 - ../Core/Src/stm32c0xx_it.c - - - - - Application/MDK-ARM - - - startup_stm32c031xx.s - 2 - startup_stm32c031xx.s - - - - - Application/OpenBootloader/App - - - app_openbootloader.c - 1 - ../OpenBootloader/App/app_openbootloader.c - - - - - Application/OpenBootloader/Target - - - common_interface.c - 1 - ../OpenBootloader/Target/common_interface.c - - - engibytes_interface.c - 1 - ../OpenBootloader/Target/engibytes_interface.c - - - flash_interface.c - 1 - ../OpenBootloader/Target/flash_interface.c - - - i2c_interface.c - 1 - ../OpenBootloader/Target/i2c_interface.c - - - iwdg_interface.c - 1 - ../OpenBootloader/Target/iwdg_interface.c - - - optionbytes_interface.c - 1 - ../OpenBootloader/Target/optionbytes_interface.c - - - otp_interface.c - 1 - ../OpenBootloader/Target/otp_interface.c - - - ram_interface.c - 1 - ../OpenBootloader/Target/ram_interface.c - - - systemmemory_interface.c - 1 - ../OpenBootloader/Target/systemmemory_interface.c - - - usart_interface.c - 1 - ../OpenBootloader/Target/usart_interface.c - - - - - Doc - - - README.md - 5 - ../README.md - - - - - Drivers/CMSIS - - - system_stm32c0xx.c - 1 - ../Core/Src/system_stm32c0xx.c - - - - - Drivers/STM32C0xx_HAL_Driver - - - stm32c0xx_hal.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c - - - 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../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c - - - stm32c0xx_hal_pwr_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c - - - stm32c0xx_hal_rcc.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c - - - stm32c0xx_hal_rcc_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c - - - stm32c0xx_hal_usart.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c - - - stm32c0xx_hal_usart_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c - - - stm32c0xx_ll_exti.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c - - - stm32c0xx_ll_gpio.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c - - - stm32c0xx_ll_i2c.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c - - - stm32c0xx_ll_pwr.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c - - - stm32c0xx_ll_rcc.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c - - - stm32c0xx_ll_usart.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c - - - - - Middlewares/OpenBootloader/Core - - - openbl_core.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Core/openbl_core.c - - - - - Middlewares/OpenBootloader/Modules/I2C - - - openbl_i2c_cmd.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/I2C/openbl_i2c_cmd.c - - - - - Middlewares/OpenBootloader/Modules/MEM - - - openbl_mem.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/Mem/openbl_mem.c - - - - - Middlewares/OpenBootloader/Modules/USART - - - openbl_usart_cmd.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/USART/openbl_usart_cmd.c - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 5 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_FULL_LL_DRIVER,USE_HAL_DRIVER,STM32C031xx + + ../Core/Inc;../OpenBootloader/App;../OpenBootloader/Target;../../../../../Drivers/CMSIS/Device/ST/STM32C0xx/Include;../../../../../Drivers/CMSIS/Include;../../../../../Drivers/STM32C0xx_HAL_Driver/Inc;../../../../../Middlewares/ST/OpenBootloader/Core;../../../../../Middlewares/ST/OpenBootloader/Modules/I2C;../../../../../Middlewares/ST/OpenBootloader/Modules/Mem;../../../../../Middlewares/ST/OpenBootloader/Modules/USART + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/Core + + + main.c + 1 + ../Core/Src/main.c + + + stm32c0xx_hal_msp.c + 1 + ../Core/Src/stm32c0xx_hal_msp.c + + + stm32c0xx_it.c + 1 + ../Core/Src/stm32c0xx_it.c + + + + + Application/MDK-ARM + + + startup_stm32c031xx.s + 2 + startup_stm32c031xx.s + + + + + Application/OpenBootloader/App + + + app_openbootloader.c + 1 + ../OpenBootloader/App/app_openbootloader.c + + + + + Application/OpenBootloader/Target + + + common_interface.c + 1 + ../OpenBootloader/Target/common_interface.c + + + engibytes_interface.c + 1 + ../OpenBootloader/Target/engibytes_interface.c + + + flash_interface.c + 1 + ../OpenBootloader/Target/flash_interface.c + + + i2c_interface.c + 1 + ../OpenBootloader/Target/i2c_interface.c + + + iwdg_interface.c + 1 + ../OpenBootloader/Target/iwdg_interface.c + + + optionbytes_interface.c + 1 + ../OpenBootloader/Target/optionbytes_interface.c + + + otp_interface.c + 1 + ../OpenBootloader/Target/otp_interface.c + + + ram_interface.c + 1 + ../OpenBootloader/Target/ram_interface.c + + + systemmemory_interface.c + 1 + ../OpenBootloader/Target/systemmemory_interface.c + + + usart_interface.c + 1 + ../OpenBootloader/Target/usart_interface.c + + + + + Doc + + + README.md + 5 + ../README.md + + + + + Drivers/CMSIS + + + system_stm32c0xx.c + 1 + ../Core/Src/system_stm32c0xx.c + + + + + Drivers/STM32C0xx_HAL_Driver + + + stm32c0xx_hal.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c + + + stm32c0xx_hal_cortex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c + + + stm32c0xx_hal_dma.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c + + + stm32c0xx_hal_exti.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c + + + stm32c0xx_hal_flash.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c + + + stm32c0xx_hal_flash_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c + + + stm32c0xx_hal_gpio.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c + + + stm32c0xx_hal_i2c.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c + + + stm32c0xx_hal_i2c_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c + + + stm32c0xx_hal_iwdg.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c + + + stm32c0xx_hal_pwr.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c + + + stm32c0xx_hal_pwr_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c + + + stm32c0xx_hal_rcc.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c + + + stm32c0xx_hal_rcc_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c + + + stm32c0xx_hal_usart.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c + + + stm32c0xx_hal_usart_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c + + + stm32c0xx_ll_exti.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c + + + stm32c0xx_ll_gpio.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c + + + stm32c0xx_ll_i2c.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c + + + stm32c0xx_ll_pwr.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c + + + stm32c0xx_ll_rcc.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c + + + stm32c0xx_ll_usart.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c + + + + + Middlewares/OpenBootloader/Core + + + openbl_core.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Core/openbl_core.c + + + + + Middlewares/OpenBootloader/Modules/I2C + + + openbl_i2c_cmd.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/I2C/openbl_i2c_cmd.c + + + + + Middlewares/OpenBootloader/Modules/MEM + + + openbl_mem.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/Mem/openbl_mem.c + + + + + Middlewares/OpenBootloader/Modules/USART + + + openbl_usart_cmd.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/USART/openbl_usart_cmd.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld index 1e1c561d..3cf3c7e7 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld @@ -1,200 +1,200 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32C031C6Tx Device from STM32C0 series -** 15Kbytes ROM -** 6Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2022 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 5K - RAM2 (xrw) : ORIGIN = 0x20001400, LENGTH = 1K - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 15K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "ROM" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >ROM - - /* The program code and other data into "ROM" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >ROM - - /* Constant data into "ROM" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >ROM - - .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >ROM - - .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >ROM - - .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >ROM - - .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >ROM - - .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >ROM - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - _siRamFunc = LOADADDR(.RamFunc); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM1 AT> ROM - - .RamFunc : - { - . = ALIGN(4); - _sRamFunc = .; /* create a global symbol at data start */ - - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _eRamFunc = .; /* define a global symbol at data end */ - - } >RAM2 AT> ROM - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM1 - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM1 - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32C031C6Tx Device from STM32C0 series +** 15Kbytes ROM +** 6Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 5K + RAM2 (xrw) : ORIGIN = 0x20001400, LENGTH = 1K + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 32K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + _siRamFunc = LOADADDR(.RamFunc); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> ROM + + .RamFunc : + { + . = ALIGN(4); + _sRamFunc = .; /* create a global symbol at data start */ + + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _eRamFunc = .; /* define a global symbol at data end */ + + } >RAM2 AT> ROM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From 4622ab9961623990c9383676015c371bd7570885 Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 18 Jul 2026 04:23:45 +0800 Subject: [PATCH 3/3] Restore minimal C031C6 review patch without EOL noise The prior follow-up commit carried the right values but rewrote line endings throughout the two C031C6 files. Rebuild the same maintainer-requested changes on top of the original file bytes so the PR diff stays reviewable. Constraint: Preserve the already accepted C092RC changes exactly as-is Rejected: Keep the earlier whole-file rewrite | obscures the actual review response Confidence: high Scope-risk: narrow Directive: If these files need more C031C6 cleanup later, do it in a separate PR with fresh justification Tested: git diff --ignore-space-at-eol HEAD^ HEAD on both files; targeted grep of OCR_RVCT4 and ROM LENGTH; static 0x8000 equals 32K address-range check Not-tested: full project builds for the IDE-specific linker/config files --- .../MDK-ARM/OpenBootloader.uvprojx | 1342 ++++++++--------- .../STM32CubeIDE/STM32C031C6TX_FLASH.ld | 398 ++--- 2 files changed, 870 insertions(+), 870 deletions(-) diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx index 7d21a0d3..3d61c551 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/MDK-ARM/OpenBootloader.uvprojx @@ -1,673 +1,673 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + NUCLEO-C031C6 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32C031C6Tx + STMicroelectronics + Keil.STM32C0xx_DFP.1.0.0 + http://www.keil.com/pack + IROM(0x08000000-0x8003BFF) IRAM(0x20000000-0x200017FF) CLOCK(8000000) CPUTYPE("Cortex-M0+") TZ + + + + 0 + + + + + + + + + + + $$Device:STM32C031C6Tx$CMSIS\SVD\STM32C031.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + NUCLEO-C031C6\Exe\ + Project + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 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../Core/Inc;../OpenBootloader/App;../OpenBootloader/Target;../../../../../Drivers/CMSIS/Device/ST/STM32C0xx/Include;../../../../../Drivers/CMSIS/Include;../../../../../Drivers/STM32C0xx_HAL_Driver/Inc;../../../../../Middlewares/ST/OpenBootloader/Core;../../../../../Middlewares/ST/OpenBootloader/Modules/I2C;../../../../../Middlewares/ST/OpenBootloader/Modules/Mem;../../../../../Middlewares/ST/OpenBootloader/Modules/USART - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - - - - - - - - - - - - - - - Application/Core - - - main.c - 1 - ../Core/Src/main.c - - - stm32c0xx_hal_msp.c - 1 - ../Core/Src/stm32c0xx_hal_msp.c - - - stm32c0xx_it.c - 1 - ../Core/Src/stm32c0xx_it.c - - - - - Application/MDK-ARM - - - startup_stm32c031xx.s - 2 - startup_stm32c031xx.s - - - - - Application/OpenBootloader/App - - - app_openbootloader.c - 1 - ../OpenBootloader/App/app_openbootloader.c - - - - - Application/OpenBootloader/Target - - - common_interface.c - 1 - ../OpenBootloader/Target/common_interface.c - - - engibytes_interface.c - 1 - ../OpenBootloader/Target/engibytes_interface.c - - - flash_interface.c - 1 - ../OpenBootloader/Target/flash_interface.c - - - i2c_interface.c - 1 - ../OpenBootloader/Target/i2c_interface.c - - - iwdg_interface.c - 1 - ../OpenBootloader/Target/iwdg_interface.c - - - optionbytes_interface.c - 1 - ../OpenBootloader/Target/optionbytes_interface.c - - - otp_interface.c - 1 - ../OpenBootloader/Target/otp_interface.c - - - ram_interface.c - 1 - ../OpenBootloader/Target/ram_interface.c - - - systemmemory_interface.c - 1 - ../OpenBootloader/Target/systemmemory_interface.c - - - usart_interface.c - 1 - ../OpenBootloader/Target/usart_interface.c - - - - - Doc - - - README.md - 5 - ../README.md - - - - - Drivers/CMSIS - - - system_stm32c0xx.c - 1 - ../Core/Src/system_stm32c0xx.c - - - - - Drivers/STM32C0xx_HAL_Driver - - - stm32c0xx_hal.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c - - - stm32c0xx_hal_cortex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c - - - stm32c0xx_hal_dma.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c - - - stm32c0xx_hal_exti.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c - - - stm32c0xx_hal_flash.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c - - - stm32c0xx_hal_flash_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c - - - stm32c0xx_hal_gpio.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c - - - stm32c0xx_hal_i2c.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c - - - stm32c0xx_hal_i2c_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c - - - stm32c0xx_hal_iwdg.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c - - - stm32c0xx_hal_pwr.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c - - - stm32c0xx_hal_pwr_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c - - - stm32c0xx_hal_rcc.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c - - - stm32c0xx_hal_rcc_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c - - - stm32c0xx_hal_usart.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c - - - stm32c0xx_hal_usart_ex.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c - - - stm32c0xx_ll_exti.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c - - - stm32c0xx_ll_gpio.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c - - - stm32c0xx_ll_i2c.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c - - - stm32c0xx_ll_pwr.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c - - - stm32c0xx_ll_rcc.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c - - - stm32c0xx_ll_usart.c - 1 - ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c - - - - - Middlewares/OpenBootloader/Core - - - openbl_core.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Core/openbl_core.c - - - - - Middlewares/OpenBootloader/Modules/I2C - - - openbl_i2c_cmd.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/I2C/openbl_i2c_cmd.c - - - - - Middlewares/OpenBootloader/Modules/MEM - - - openbl_mem.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/Mem/openbl_mem.c - - - - - Middlewares/OpenBootloader/Modules/USART - - - openbl_usart_cmd.c - 1 - ../../../../../Middlewares/ST/OpenBootloader/Modules/USART/openbl_usart_cmd.c - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 5 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_FULL_LL_DRIVER,USE_HAL_DRIVER,STM32C031xx + + ../Core/Inc;../OpenBootloader/App;../OpenBootloader/Target;../../../../../Drivers/CMSIS/Device/ST/STM32C0xx/Include;../../../../../Drivers/CMSIS/Include;../../../../../Drivers/STM32C0xx_HAL_Driver/Inc;../../../../../Middlewares/ST/OpenBootloader/Core;../../../../../Middlewares/ST/OpenBootloader/Modules/I2C;../../../../../Middlewares/ST/OpenBootloader/Modules/Mem;../../../../../Middlewares/ST/OpenBootloader/Modules/USART + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/Core + + + main.c + 1 + ../Core/Src/main.c + + + stm32c0xx_hal_msp.c + 1 + ../Core/Src/stm32c0xx_hal_msp.c + + + stm32c0xx_it.c + 1 + ../Core/Src/stm32c0xx_it.c + + + + + Application/MDK-ARM + + + startup_stm32c031xx.s + 2 + startup_stm32c031xx.s + + + + + Application/OpenBootloader/App + + + app_openbootloader.c + 1 + ../OpenBootloader/App/app_openbootloader.c + + + + + Application/OpenBootloader/Target + + + common_interface.c + 1 + ../OpenBootloader/Target/common_interface.c + + + engibytes_interface.c + 1 + ../OpenBootloader/Target/engibytes_interface.c + + + flash_interface.c + 1 + ../OpenBootloader/Target/flash_interface.c + + + i2c_interface.c + 1 + ../OpenBootloader/Target/i2c_interface.c + + + iwdg_interface.c + 1 + ../OpenBootloader/Target/iwdg_interface.c + + + optionbytes_interface.c + 1 + ../OpenBootloader/Target/optionbytes_interface.c + + + otp_interface.c + 1 + ../OpenBootloader/Target/otp_interface.c + + + ram_interface.c + 1 + ../OpenBootloader/Target/ram_interface.c + + + systemmemory_interface.c + 1 + ../OpenBootloader/Target/systemmemory_interface.c + + + usart_interface.c + 1 + ../OpenBootloader/Target/usart_interface.c + + + + + Doc + + + README.md + 5 + ../README.md + + + + + Drivers/CMSIS + + + system_stm32c0xx.c + 1 + ../Core/Src/system_stm32c0xx.c + + + + + Drivers/STM32C0xx_HAL_Driver + + + stm32c0xx_hal.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c + + + stm32c0xx_hal_cortex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c + + + stm32c0xx_hal_dma.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c + + + stm32c0xx_hal_exti.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c + + + stm32c0xx_hal_flash.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c + + + stm32c0xx_hal_flash_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c + + + stm32c0xx_hal_gpio.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c + + + stm32c0xx_hal_i2c.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c + + + stm32c0xx_hal_i2c_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c + + + stm32c0xx_hal_iwdg.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c + + + stm32c0xx_hal_pwr.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c + + + stm32c0xx_hal_pwr_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c + + + stm32c0xx_hal_rcc.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c + + + stm32c0xx_hal_rcc_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c + + + stm32c0xx_hal_usart.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c + + + stm32c0xx_hal_usart_ex.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c + + + stm32c0xx_ll_exti.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c + + + stm32c0xx_ll_gpio.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c + + + stm32c0xx_ll_i2c.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c + + + stm32c0xx_ll_pwr.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c + + + stm32c0xx_ll_rcc.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c + + + stm32c0xx_ll_usart.c + 1 + ../../../../../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c + + + + + Middlewares/OpenBootloader/Core + + + openbl_core.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Core/openbl_core.c + + + + + Middlewares/OpenBootloader/Modules/I2C + + + openbl_i2c_cmd.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/I2C/openbl_i2c_cmd.c + + + + + Middlewares/OpenBootloader/Modules/MEM + + + openbl_mem.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/Mem/openbl_mem.c + + + + + Middlewares/OpenBootloader/Modules/USART + + + openbl_usart_cmd.c + 1 + ../../../../../Middlewares/ST/OpenBootloader/Modules/USART/openbl_usart_cmd.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld index 3cf3c7e7..111ed6c6 100644 --- a/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld +++ b/Projects/NUCLEO-C031C6/Applications/OpenBootloader/STM32CubeIDE/STM32C031C6TX_FLASH.ld @@ -1,200 +1,200 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32C031C6Tx Device from STM32C0 series -** 15Kbytes ROM -** 6Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2022 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 5K - RAM2 (xrw) : ORIGIN = 0x20001400, LENGTH = 1K +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32C031C6Tx Device from STM32C0 series +** 15Kbytes ROM +** 6Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 5K + RAM2 (xrw) : ORIGIN = 0x20001400, LENGTH = 1K ROM (rx) : ORIGIN = 0x08000000, LENGTH = 32K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "ROM" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >ROM - - /* The program code and other data into "ROM" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >ROM - - /* Constant data into "ROM" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >ROM - - .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >ROM - - .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >ROM - - .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >ROM - - .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >ROM - - .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >ROM - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - _siRamFunc = LOADADDR(.RamFunc); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM1 AT> ROM - - .RamFunc : - { - . = ALIGN(4); - _sRamFunc = .; /* create a global symbol at data start */ - - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _eRamFunc = .; /* define a global symbol at data end */ - - } >RAM2 AT> ROM - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM1 - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM1 - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + _siRamFunc = LOADADDR(.RamFunc); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> ROM + + .RamFunc : + { + . = ALIGN(4); + _sRamFunc = .; /* create a global symbol at data start */ + + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _eRamFunc = .; /* define a global symbol at data end */ + + } >RAM2 AT> ROM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +}