Hello everyone. I am having troubles with LVS, and do not manage to get a result with no mismatches. Reading the previous issues, I thought the problem might be caused by the magic version, so I tried different older versions with no success. Since I am not familiar with OpenRAM, I really don't know how to approach this. I am trying to compile this small true dual port memory (I forgot to change `ports_human`, so the output files have `1rw1r` in the name): ```python word_size = 16 num_words = 64 human_byte_size = "{:.0f}kbits".format((word_size * num_words)/1024) write_size = 8 num_rw_ports = 2 num_r_ports = 0 num_w_ports = 0 num_spare_rows = 2 num_spare_cols = 1 ports_human = '1rw1r' num_threads = 4 inline_lvsdrc=True import os exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read()) ``` And this is the error I got: ``` ERROR: file magic.py: line 385: sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array LVS mismatch (results in /tmp/openram_dario_8205_temp/sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array.lvs.report) ERROR: file hierarchy_design.py: line 79: LVS failed for sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array with 2 errors(s) ``` Here are the LVS-related reports I got: [lvs_reports.zip](https://github.com/user-attachments/files/28584371/lvs_reports.zip) I also tried with different size and port configurations and the LVS keeps failing. I am working on the commit https://github.com/VLSIDA/OpenRAM/commit/d309a25c4c30893c6771ab736a666b145289d985 Thanks a lot in advance.