[AMDGPU] Perf: set force-vector-interleave=8 in JIT pipeline#772
[AMDGPU] Perf: set force-vector-interleave=8 in JIT pipeline#772paveltc wants to merge 1 commit into
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Co-authored-by: Cursor <cursoragent@cursor.com>
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| struct AMDGPUSetLoopInterleavePass | ||
| : public llvm::PassInfoMixin<AMDGPUSetLoopInterleavePass> { |
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AGENTS.md requires minimizing contact area for new/experimental features; this AMDGPU-specific pass is defined in the shared llvm_context_pass.h outside the AMDGPU guard, so every CPU/CUDA LLVM include site now compiles and depends on the new LoopInfo/LoopPassManager code even though only jit_amdgpu.cpp registers it. Please keep the pass private to the AMDGPU JIT file, or at least under QD_WITH_AMDGPU, to avoid expanding the common LLVM surface area for this backend knob.
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Summary
Set
-force-vector-interleave=8viallvm::cl::ParseCommandLineOptionsincompile_module_to_hsacoon first use (guarded bystd::call_once).Vector interleaving allows the LLVM backend to unroll and software-pipeline
loops, keeping more functional units busy across the wider CDNA wavefronts.
The value 8 matches the recommended setting for MI200/MI300 series cards.
No correctness change. Verified with a full
not slowtest suite run onAMD MI300X with
QD_AMDGPU_FORCE_PERMLANE64_FALLBACK=1:4166 passed, 0 AMD-related failures (1 pre-existing flaky x64 timing
test unrelated to this change).
Ported from ROCm#8.