x86 L1 Data Cache Simulator#3
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This commit introduces a detailed simulation of an x86 L1 Data Cache. - Capacity: 32KB - Line Size: 64 Bytes - Associativity: 8-way - Policy: Write-back, LRU Replacement - Protocol: MESI (Single core implementation) Includes `SimulatedArray` helper for Python integration and `verify_cache.py` for testing. Co-authored-by: bugparty <1510776+bugparty@users.noreply.github.com>
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📝 WalkthroughWalkthroughAdds a new in-process L1 data cache simulation (32 KB, 8-way, 64 B lines) with MainMemory, MESI-like states, LRU replacement, write-back behavior, a SimulatedArray abstraction, unit tests, documentation, and visualization utilities for analysis. Changes
Sequence Diagram(s)sequenceDiagram
participant App as Application
participant Cache as L1Cache
participant Mem as MainMemory
App->>Cache: read/write(address, size, data?)
activate Cache
Cache->>Cache: decompose address -> tag, set_index, offset
Cache->>Cache: _find_line(set_index, tag)
alt Hit
Cache->>Cache: update LRU / state (on write)
Cache-->>App: return data / ack
else Miss
Cache->>Cache: _get_victim(set_index)
alt Victim state == M
Cache->>Mem: write_back_block(evict_addr, block)
activate Mem
Mem-->>Cache: ack
deactivate Mem
end
Cache->>Mem: read_block(block_addr)
activate Mem
Mem-->>Cache: block_data
deactivate Mem
Cache->>Cache: install line, set state (E/M), update LRU
Cache-->>App: return data / ack
end
deactivate Cache
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes Poem
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✅ Passed checks (2 passed)
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| # Check if cache has an allocator, otherwise use a static global counter on class or something | ||
| # For now, start at 0x1000 and increment? | ||
| # Let's just default to 0x1000 if user doesn't specify, but warn. | ||
| # Ideally the user manages layout. | ||
| self.base_addr = 0x1000 |
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When base_addr is omitted, every SimulatedArray defaults to 0x1000, so two arrays created without an explicit base will alias the same memory region. That causes writes in one array to overwrite the other and corrupt cache statistics or data reads (e.g., creating two arrays back-to-back and writing to both yields cross-contamination). Consider tracking a monotonically increasing allocator (or reserving length * item_size) so each default allocation gets a unique base.
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Actionable comments posted: 2
🤖 Fix all issues with AI agents
In `@cpu_l1_cache.py`:
- Around line 85-154: The access method lacks bounds validation for offset+size
against self.line_size causing IndexError or silent truncation; add an early
check at the start of access (in function access) that computes
tag,set_index,offset = self._get_addr_components(address) then verifies offset +
size <= self.line_size and if not either raise a clear ValueError (e.g. "access
spans cache line") or split the request into multiple cache-line accesses;
ensure this single check prevents out-of-bounds access in the write loop (where
line.data[offset + i] / victim.data[offset + i] is written) and guarantees the
read return slices (line.data[offset:offset+size] /
victim.data[offset:offset+size]) always contain the requested bytes.
In `@verify_cache.py`:
- Around line 14-16: The loop in verify_cache.py reads values into an unused
variable `val` (for i in range(32): val = arr[i]); change the assignment to use
the conventional discard name so intent is clear—assign the read to `_` (e.g.,
`_ = arr[i]`) or otherwise avoid creating `val`—so the read remains for cache
side effects but no unused-variable remains; update the loop in the same
function/block that references `arr` and `val`.
🧹 Nitpick comments (3)
cpu_l1_cache.py (3)
67-72: Minor style: unused loop variable.The loop index
iis not used within the loop body.Suggested fix
def _find_line(self, set_index, tag): cache_set = self.sets[set_index] - for i, line in enumerate(cache_set): + for line in cache_set: if line.state != 'I' and line.tag == tag: return line return None
74-83: Rename ambiguous variablel.The variable
lin the lambda can be confused with1orIin certain fonts.Suggested fix
# Use LRU - victim = min(cache_set, key=lambda l: l.last_accessed) + victim = min(cache_set, key=lambda line: line.last_accessed) return victim
123-131: Consider handling 'S' state eviction for completeness.Eviction of lines in 'M' and 'E' states are counted, but 'S' state (Shared) is not handled. While the comment notes 'S' shouldn't occur in single-core mode, adding this case would make the MESI implementation complete if multi-core support is added later.
Suggested fix
if victim.state == 'M': # Write Back self.stats['evictions'] += 1 self.stats['write_backs'] += 1 victim_addr = (victim.tag * self.num_sets * self.line_size) + (set_index * self.line_size) self.memory.write(victim_addr, victim.data) elif victim.state == 'E': - # Clean eviction - self.stats['evictions'] += 1 + # Clean eviction + self.stats['evictions'] += 1 + elif victim.state == 'S': + # Clean eviction (shared line) + self.stats['evictions'] += 1
| # Read all | ||
| for i in range(32): | ||
| val = arr[i] |
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Unused variable val.
The value is read for its cache side effects but never used. Assign to _ to indicate intentional discard.
Suggested fix
# Read all
for i in range(32):
- val = arr[i]
+ _ = arr[i] # Read for cache side effects📝 Committable suggestion
‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.
| # Read all | |
| for i in range(32): | |
| val = arr[i] | |
| # Read all | |
| for i in range(32): | |
| _ = arr[i] # Read for cache side effects |
🧰 Tools
🪛 Ruff (0.14.14)
16-16: Local variable val is assigned to but never used
Remove assignment to unused variable val
(F841)
🤖 Prompt for AI Agents
In `@verify_cache.py` around lines 14 - 16, The loop in verify_cache.py reads
values into an unused variable `val` (for i in range(32): val = arr[i]); change
the assignment to use the conventional discard name so intent is clear—assign
the read to `_` (e.g., `_ = arr[i]`) or otherwise avoid creating `val`—so the
read remains for cache side effects but no unused-variable remains; update the
loop in the same function/block that references `arr` and `val`.
- Added `CACHE_SPECS.md` detailing architecture specifications. - Updated `cpu_l1_cache.py` to track access history and per-address counts. - Created `cache_viz.py` to generate miss rate plots, 2D heatmaps, and 3D access plots. - Created `verify_viz.py` to demonstrate visualization generation. Co-authored-by: bugparty <1510776+bugparty@users.noreply.github.com>
Ensures that low-level access calls do not span across cache line boundaries, raising a ValueError if they do. This enforces the design where `read` and `write` helper methods are responsible for splitting requests. Previous changes included: - x86 L1 Cache Simulator Visualization Tools - CACHE_SPECS.md - Updated cpu_l1_cache.py to track access history and per-address counts. - Created cache_viz.py and verify_viz.py. Co-authored-by: bugparty <1510776+bugparty@users.noreply.github.com>
1 participant
Implemented a Python-based CPU L1 Cache simulator mimicking x86 architecture features (32KB, 8-way, 64B line, Write-back, MESI). Added a
SimulatedArrayclass to allow user code to interface with the simulated memory and track access patterns. Verification script included.PR created automatically by Jules for task 4675641926694390111 started by @bugparty
Summary by CodeRabbit
New Features
Visualization
Documentation
Tests
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