Convert -Ctarget-cpu into a target-modifier for AVR, AMDGCN and NVPTX #150732
Convert -Ctarget-cpu into a target-modifier for AVR, AMDGCN and NVPTX #150732kulst wants to merge 2 commits into
-Ctarget-cpu into a target-modifier for AVR, AMDGCN and NVPTX #150732Conversation
-Ctarget-cpu a target-modifier on NVPTX
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@rustbot label: +O-NVPTX |
-Ctarget-cpu a target-modifier on NVPTX-Ctarget-cpu into a target-modifier on NVPTX
-Ctarget-cpu into a target-modifier on NVPTX-Ctarget-cpu into a target-modifier for NVPTX
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Some changes occurred in src/doc/rustc/src/platform-support cc @Noratrieb These commits modify compiler targets. |
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r? @nnethercote rustbot has assigned @nnethercote. Use |
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r? @bjorn3 as you suggested this change. |
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It works out really nice with -CTarget-cpu being able to be a target modifier. It would be nice to know what the plan was with the ptx isa version as well. I asked that question here |
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I can't vouch for the implementation, but the approach sounds good. :) Cc @Darksonn |
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I have added some explanation of why |
| pub(super) fn target_cpu( | ||
| sess: &Session, | ||
| l: &TargetModifier, | ||
| r: Option<&TargetModifier>, | ||
| ) -> bool { | ||
| if sess.target.cpu_is_target_modifier { | ||
| if let Some(r) = r { | ||
| return l.extend().tech_value == r.extend().tech_value; | ||
| } else { | ||
| return false; |
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What happens if -Ctarget-cpu appears multiple times on the command line? Please add a test.
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The value of the last appearance in matches is used. In practice this is probably the value of -Ctarget-cpus last appearance in the command line arguments of the rustc invocation.
Will add a test soon, but I am asking myself what is the intended behavior? I assume we should error if a target-modifier appears more than once, would you agree?
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At the very least we have to ensure that whatever values rustc actually uses and what is recorded as target modifier are the same.
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Last argument taking precedence is the desired functionality:
Corresponding MCP
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Behavior as per MCP is fine. Whichever value ends up being used should be tracked and verified.
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Is checked now by tests/run-make/target-cpu-is-target-modifier/rmake.rs
Does that match what you had in mind?
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Some changes occurred to the intrinsics. Make sure the CTFE / Miri interpreter cc @rust-lang/miri, @RalfJung, @oli-obk, @lcnr The reflection data structures are tied exactly to the implementation cc @oli-obk
Some changes occurred in tests/ui/stack-protector cc @rust-lang/project-exploit-mitigations, @rcvalle Some changes occurred to the CTFE / Miri interpreter cc @rust-lang/miri Some changes occurred in src/tools/clippy cc @rust-lang/clippy Some changes occurred to the CTFE machinery |
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cc @bjorn3
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I've made the requested changes and rebased on top of the current main branch. |
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I have revised the tests and integrated the other suggestions.
@rustbot ready |
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- Boolean target modifiers are now mentioned without a trailing `=` in the messages. - Wording improved for unset target modifiers.
…and NVPTX For AVR, AMDGCN, and NVPTX, crates built with different target CPU values are not generally link-compatible. Add a `requires_consistent_cpu` flag to the target spec and enable it for these targets. When the flag is set, treat `-Ctarget-cpu` as a target modifier and require all linked crates to agree on its value. Reject `-Ctarget-cpu=native` before codegen for targets that set `requires_consistent_cpu` to true. Also do not include `native` in the printed `target-cpus` list for such targets. Add tests covering: - which built-in targets set `requires-consistent-cpu` - cross-crate behavior with and without `requires-consistent-cpu` - that an omitted `-Ctarget-cpu` compares equal to an explicitly specified default CPU - rejection and printing behavior for `native` - precedence of repeated `-Ctarget-cpu` flags in metadata comparison and LLVM IR
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This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed. Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers. |
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Crates built for AVR, AMDGCN and NVPTX that specify different values for
-Ctarget-cpucannot be soundly linked together.This PR attempts to make
rustcensure that no crates with disagreeing values for-Ctarget-cpuare linked together. This is achieved by converting-Ctarget-cpuinto a target-modifier depending on--target.To do this, the consistency check for
-Ctarget-cpuconsiders mismatching values as inconsistent only for targets for which the new flagrequires_consistent_cpuis set in their target spec.Why should
-Ctarget-cpube a target-modifier fornvptx?PTX is a single-module contract
PTX requires a binary to start with .version (`ptx$$`) then .target (`sm_$$`). If the ptx contains instructions that are not supported by either .version or .target, the binary is ill-formed and will be rejected by ptxas. The concept of features that can be mixed and matched in a binary does not exist for nvptx and is therefore not supported by LLVM.
It prevents the production of bitcode that cannot be codegen'd after linking
A target modifier should prevent configurations that are not composable across crates when those crates are linked together. The most prominent example is when enabling a target feature changes the ABI, making cross-crate calls inherently unsound.
In the case of nvptx, ABI mismatch is (at least for now) not the core problem motivating target modifiers. NVIDIA’s documented PTX calling convention has remained stable since ptx20.
However, in the current state it is possible to produce bitcode that cannot be codegen'd after linking, because some operations are only lowerable for sufficiently new SM/PTX levels. In the best case this results in an LLVM error during the final llc step, but this is not something we should rely on for correctness.
nvptx has a special compilation pipeline where instead of linking the final PTX object, instead LLVM bitcode is linked. The resulting artifact is then compiled in one invocation.
Now consider crate A which is independently compiled into bitcode with the following rustc arguments:
Crate A is a dependency of crate B. In the rustc invocation of crate B
This should now ideally create an LLVM error, because the linked bitcode contains code paths that were selected under
sm_70assumptions but the final NVPTX codegen is targetingsm_60, where those operations are not lowerable. An LLVM error here is better than silent miscompilation, but it’s not a promise we should rely on.A real example where this could happen is the lowering of atomic loads and stores with non-relaxed orderings, which is known to depend on the selected SM level.
Why should
-Ctarget-cpube a target-modifier foramdgcnandavr?Previous discussions about the topic can be found here and here.
I also created a Zulip discussion.
I am unsure if a MCP is needed before proceeding. If you think so please let me know.
Creating target-modifiers for NVPTX target-features is to be done in a follow-up.
cc @kjetilkjeka as target maintainer for NVPTX
cc @Flakebi as target maintainer for amdgcn
cc @Patryk27 as target maintainer for AVR
cc @RalfJung you were very involved in the discussions so far
Target modifier tracking issue: #136966