Open, reproducible, local-first silicon tooling — the EDA toolchain, sign-off engines, and open PDKs behind Vyges™.

vyges-tools is the home for the tooling that turns RTL into silicon: the Vyges command-line interface, the Loom open EDA sign-off suite, reproducible from-source builds of the open-source EDA tools, and a tool-agnostic catalog of open process design kits. Everything here runs on your machine — no cloud lock-in, no per-seat licenses — and is pinned so a build today reproduces the same result tomorrow.

One binary for the whole flow: install and manage IP, PDKs, and the Loom sign-off engines, then drive them from the command line or an MCP-aware assistant.

• cli — prebuilt binaries + one-line installers (macOS · Linux · Windows), a Homebrew tap, and the catalog / PDK / Loom-engine installers.
• Docs: https://docs.vyges.com

Loom is a suite of fast, deterministic, local sign-off engines that share one parse-once design database. Run each as vyges loom <engine>.

• Timing & SI — sta-si: WNS/TNS sign-off with crosstalk + statistical OCV
• Power, IR & thermal — power · em-ir · thermal
• Physical verification — drc · lvs · extract (routed layout → SPEF)
• Characterization — char: SPICE + PDK models → Liberty (NLDM + CCS)
• Timing ECOs — hold-fix · buffer-insert · resize · vt-swap
• Foundation — loom: shared readers (Verilog · Liberty · SDC · SPEF) + in-memory design database

More engines (CDC, glitch, LEC, layout, geometry, remap, structured events) live across the org — browse the repository list.

• See it run → the AI-driven sign-off dashboard: a stock, general-purpose LLM drives the real Loom engines through vyges mcp, picking each tool and forming its arguments from the engine descriptors alone.
• Product page: https://vyges.com/products/loom

Headless, multi-arch (amd64 + arm64) builds of the open-source EDA tools — pinned to exact upstream commits, built from source on CI, published to GHCR.

• vyges-yosys — Yosys + ABC + OpenSTA (synthesis + timing)
• vyges-openroad — OpenROAD (RTL → GDS)
• vyges-klayout — headless, Qt-free KLayout + GDS renderer
• vyges-ngspice — OSDI / OpenVAF-enabled ngspice
• vyges-sim — Verilator + cocotb simulation substrate
• vybox-eda — one light container composing them all, for digital + analog + mixed-signal flows

A tool-agnostic catalog of open process design kits, presented uniformly so any flow can consume them.

• pdk-catalog — the index + full PDK descriptors
• pdk-releases — Vyges-built, ciel-compatible open-PDK releases
• Mirrors: sky130 (open_pdks) · gf180mcu · IHP SG13G2 · IHP SG13CMOS-5L · ASAP7 · Nangate45 · ICsprout55

vyges-tools is operated by TrustStix Inc (California, USA — C Corporation). The tools here are free and open; operational costs (build infrastructure, hosting, curation) are absorbed by TrustStix. We treat this toolchain as public infrastructure for the open-silicon ecosystem.

• Main site: https://vyges.com
• Products: https://vyges.com/products
• Loom: https://vyges.com/products/loom
• Loom testbench (live): https://vyges.github.io/vyges-loom-testbench/
• VyCatalog: https://vyges.com/products/vycatalog
• Docs: https://docs.vyges.com
• Contact: https://vyges.com/contact
• Sponsor: https://github.com/sponsors/vyges-ip