Algebraic enhancements for GEMM & AI accelerators

Minimal TPU implementation with 8x8 systolic array and PyTorch integration

A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication

Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.

SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations

Modular systolic array with software interface

course materials of Hardware Accelerator course, a practical course on hardware accelerators: CNN accelerators, systolic arrays, CUDA, quantization, pruning, Vivado, Timeloop/Accelergy, and MAESTRO. Spring 2025, Shahid Beheshti University

Hardware accelerator for 2D convolution using an 8×8 weight-stationary systolic array with split-kernel support, dual-port SRAM architecture, and DMA-based streaming

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

Small-scale FPGA-based Neural Processing Unit (CNN Accelerator) with INT8 systolic array matrix multiplication in Verilog.

A high-performance INT8 Matrix Multiplication Accelerator implemented in pure Verilog, optimized for Edge AI inference on Xilinx Kria KV260 (Zynq UltraScale+ MPSoC).

Generic Multiplication Accelerator on FPGA

High-performance systolic array computing framework with AI agents and medical compliance.

INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis

Deadline-constrained SCALE-Sim and Accelergy experiment for image-processing systolic arrays

4×4 7-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.

An AXI-native 8x8 systolic array accelerator in Verilog. Features pure dataflow pipelining, Q-format fixed-point arithmetic, and hardware validation on the Kria KV260 FPGA.

Three Logisim implementations of matrix multiplication — Standard, Systolic TPU, and Tiling. Built from scratch in digital logic.

Hardware-level AI Matrix Multiplication Accelerator (Systolic Array) in SystemVerilog using AXI4-Stream, verified via Python & Cocotb co-simulation.

𓁰 PtahCore — open-source FP8 tensor accelerator, RTL→GDSII on open 7nm ASAP7, 100% open toolchain